AT80C32X2-RLTUL Atmel, AT80C32X2-RLTUL Datasheet - Page 20

• Manufacturer Part Number: AT80C32X2-RLTUL
• Description: IC 8051 MCU ROMLESS 44VQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C32X2-RLTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 30/20MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin VQFP
• Programmable Memory: 0 Bytes
• Timers: 4-8-bit, 3-16-bit
• Voltage, Range: 2.7-7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

20
TS8xCx2X2
Table 9. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
Mnemonic Description
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
RI
SM1
TI
6
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure
8. in the other modes.
SM0 SM1
0
0
1
1
SM2
5
0
1
0
1
Mode Description
0
1
2
3
REN
4
Shift Register F
8-bit UART
9-bit UART
9-bit UART
TB8
3
Baud Rate
Variable
F
Variable
XTAL
XTAL
/12 (/6 in X2 mode)
/64 or F
RB8
2
XTAL
/32 (/32, /16 in X2 mode)
TI
1
4184G–8051–09/06
RI
0