DSPIC33FJ64MC510-I/PT Microchip Technology, DSPIC33FJ64MC510-I/PT Datasheet - Page 138
![IC DSPIC MCU/DSP 64K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64MC510-I/PT
Manufacturer Part Number
DSPIC33FJ64MC510-I/PT
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.PIC24HJ12GP201-ISO.pdf
(84 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ64MC510-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
85
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ64MC510-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA330013 PDF datasheet
- PIC24HJ12GP201-ISO PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- DSPIC33FJ64MC506-IPT PDF datasheet #4
- Current page: 138 of 370
- Download datasheet (6Mb)
dsPIC33F
FIGURE 7-1:
7.1
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
• A 16-bit DMA Channel IRQ Select register
• A 16-bit DMA RAM Primary Start Address register
• A 16-bit DMA RAM Secondary Start Address
• A 16-bit DMA Peripheral Address register
• A 10-bit DMA Transfer Count register (DMAx-
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write colli-
sion flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong
mode status.
The
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB will read the con-
tents of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
DS70165E-page 136
(DMAxCON)
(DMAxREQ)
(DMAxSTA)
register (DMAxSTB)
(DMAxPAD)
CNT)
Note: CPU and DMA address buses are not shown for clarity.
SRAM
DMAxCON,
DMAC Registers
SRAM X-Bus
CPU
DMAxREQ,
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
Ready
PORT 2
DMAxPAD
DMA DS Bus
and
Preliminary
DMA Controller
an IECx register in the interrupt controller, and the cor-
responding interrupt priority control bits (DMAxIP) are
located in an IPCx register in the interrupt controller.
7.2
Each DMA channel has its own status and control reg-
ister (DMAxCON) that is used to configure the channel
to support the following operating modes:
• Word or byte size data transfers
• Peripheral to DMA RAM or DMA RAM to
• Post-increment or static DMA RAM address
• One-shot or continuous block transfers
• Auto-switch between two start addresses after
• Force a single DMA transfer (Manual mode)
Each DMA channel can be independently configured
to:
• Select from one of 20 DMA request sources
• Manually enable or disable the DMA channel
• Interrupt the CPU when the transfer is half or fully
DMA channel interrupts are routed to the interrupt con-
troller module and enabled through associated enable
flags.
The channel DMA RAM and peripheral write collision
Faults are combined into a single DMAC error trap
(Level 10) and are not maskable. Each channel has
DMA RAM write collision (XWCOLx) and peripheral
peripheral transfers
each transfer complete (Ping-Pong mode)
complete
Channels
DMA
Peripheral Indirect Address
DMAC Operating Modes
Peripheral 1
CPU
Ready
DMA
© 2007 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA
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