PIC16F716-I/ML Microchip Technology, PIC16F716-I/ML Datasheet - Page 285
PIC16F716-I/ML
Manufacturer Part Number
PIC16F716-I/ML
Description
IC PIC MCU FLASH 2KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F716-ISO.pdf
(136 pages)
4.PIC16F716-ISO.pdf
(12 pages)
Specifications of PIC16F716-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F716-ISO PDF datasheet #3
- PIC16F716-ISO PDF datasheet #4
- Current page: 285 of 688
- Download datasheet (3Mb)
17.3
17.3.1
1997 Microchip Technology Inc.
Operation
SPI Mode
The SPI mode allows 8-bits of data to be synchronously transmitted and received simulta-
neously. All four modes of SPI are supported. To accomplish communication, typically three pins
are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be specified. This is done by programming the
appropriate control bits in the SSPCON1 register (SSPCON1<5:0>) and SSPSTAT<7:6>. These
control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase (middle or end of data output time)
• Clock edge (output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Figure 17-4
Figure 17-4:
shows the block diagram of the SSP module, when in SPI mode.
SSP Block Diagram (SPI Mode)
SDO
SCK
SDI
SS
Preliminary
Read
SS Control
Select
SMP:CKE
Edge
Enable
bit0
Select
Edge
SSPBUF reg
TRIS bit
Data to TX/RX in SSPSR
2
SSPM3:SSPM0
SSPSR reg
Clock Select
Section 17. MSSP
4
2
Write
Prescaler
4, 16, 64
clock
shift
TMR2 output
data bus
Internal
2
T
OSC
DS31017A-page 17-9
17
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