AT89C5130A-RDTIM Atmel, AT89C5130A-RDTIM Datasheet - Page 147

• Manufacturer Part Number: AT89C5130A-RDTIM
• Description: IC 8051 MCU FLASH 16K USB 64VQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-RDTIM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

4337K–USB–04/08
Table 21-13. UEPRST Register
Reset Value = 00h
Bit Number
7
7
6
5
4
3
2
1
0
-
Mnemonic
EP6RST
EP6RST
EP5RST
EP4RST
EP3RST
EP2RST
EP1RST
EP0RST
UEPRST (S:D5h)
USB Endpoint FIFO Reset Register
Bit
6
-
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 6 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset
or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP5RST
5
EP4RST
4
EP3RST
3
AT89C5130A/31A-M
EP2RST
2
EP1RST
1
EP0RST
0
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