AT89LP2052-16XU Atmel, AT89LP2052-16XU Datasheet - Page 4

• Manufacturer Part Number: AT89LP2052-16XU
• Description: IC 8051 MCU FLASH 2K 20TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP2052-16XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Improved Performance
4
Key Advantages
AT89LP microcontrollers have the following key advantages:
The Atmel AT89LP family is based on a low-power, high-performance 8-bit single-cycle
8051 core. The classic 8051 CPU requires 12 clock cycles for every instruction byte fetch,
whereas the new AT89LP CPU employs a simple two-stage pipeline that requires only one
clock cycle for every byte fetch. Instructions run on the AT89LP family need only 1 to 4
clock cycles to complete, whereas the classic 8051 requires 12 to 48 clocks, thereby
providing 6-12 times or higher throughput than the classic 8051. Seventy percent of the
instructions execute in the same number of clock cycles as the number of bytes to be
fetched, allowing up to 1 MIPS per MHz of system frequency. At 20 MHz maximum clock
frequency the AT89LP core is capable of 20 MIPS throughput. In comparison, the classic
8051 architecture delivers less than 2 MIPS at 20 MHz. Figure 2 shows a comparison of
cycles per instruction between a standard 8051 and an AT89LP microcontroller.
Binary compatibility with the industry standard MCS®51 instruction set
Access to a wide range of existing code libraries and development tools from several
vendors
Lower power consumption and reduced EMI for the same throughput as classic 8051s
6x to 12x quicker interrupt response times and faster pin toggling than classic 8051s
Fully static CMOS logic implementation driven by a single system clock
Totally deterministic response at 20 MIPS (no cache memory)
Boolean processor (bit set/reset read-modify-write instructions execute in two-cycles)
Power saving modes of operation (Idle and Power-down) with multiple interrupt-based
wake-up sources
Fast programming time using Page Mode
In-Application Programming for the added power of self-modifying code
DSP-grade CPU speed using built-in hardware multiplier and fast dual data pointers
Small footprints for space constrained applications
Wide voltage operating range to meet a variety of needs
Upward migration path to devices with larger memories or more I/Os
On-Chip Debug system allows development of firmware within the target system
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