PIC16LF818T-I/MLTSL Microchip Technology, PIC16LF818T-I/MLTSL Datasheet - Page 56
![IC PIC MCU FLASH 1KX14 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF818T-I/MLTSL
Manufacturer Part Number
PIC16LF818T-I/MLTSL
Description
IC PIC MCU FLASH 1KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(176 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16LF818T-I/MLTSL
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LF818TIMLTSL
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- Current page: 56 of 176
- Download datasheet (4Mb)
PIC16F818/819
6.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 T
a small RC delay of 20 ns) and low for at least 2 T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.4
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
REGISTER 6-1:
DS39598E-page 54
Using Timer0 with an
External Clock
Prescaler
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h)
bit 7
RBPU
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit
-n = Value at POR
Bit Value TMR0 Rate WDT Rate
Note:
R/W-1
RBPU
000
001
010
011
100
101
110
111
:
PORTB Pull-up Enable bit
To avoid an unintended device Reset, the instruction sequence shown in the
“PICmicro
executed when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.
INTEDG
R/W-1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
®
OSC
Mid-Range MCU Family Reference Manual” (DS33023) must be
R/W-1
T0CS
(and
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
W = Writable bit
‘1’ = Bit is set
R/W-1
T0SE
Timer0 module means that there is no prescaler for the
Watchdog Timer and vice versa. This prescaler is not
readable or writable (see Figure 6-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
Note:
1, x....etc.) will clear the prescaler. When
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
PSA
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
R/W-1
2004 Microchip Technology Inc.
PS2
x = Bit is unknown
R/W-1
PS1
R/W-1
PS0
bit 0
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