DSPIC30F6012A-20I/PT Microchip Technology, DSPIC30F6012A-20I/PT Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F6012A-20I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: DSPIC30F6012A20IP

dsPIC30F6011A/6012A/6013A/6014A
1. Module: MAC Class Instructions with ±4
2. Module: CPU –
EXAMPLE 1:
DS80242C-page 2
L0:daw.b
L1: ....
Sequential MAC class instructions, which prefetch
data from Y data space using ±4 address modifica-
tion, will cause an address error trap. The trap
occurs only when all of the following conditions are
true:
1. Two sequential MAC class instructions (or a
2. Both instructions prefetch data from Y data
3. Neither instruction uses an accumulator write-
Work around
The problem described above can be avoided by
using any of the following methods:
1. Inserting any other instruction between the two
2. Adding an accumulator write-back (a dummy
3. Do not use the + = 4 or – = 4 address
4. Do not prefetch data from Y data space.
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the state of the Carry bit prior to executing
the DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b instruc-
tion. Example 1 shows how the application should
process the Carry bit during a BCD addition
operation.
.include "p30fxxxx.inc"
.......
mov.b
mov.b
add.b
bra
daw.b
bset.b
bra
MAC class instruction executed in a REPEAT or
DO loop) that prefetch from Y data space.
space using the + = 4 or – = 4 address
modification.
back.
MAC class instructions.
write-back if needed) to either of the MAC class
instructions.
modification.
#0x80, w0
#0x80, w1
w0, w1, w2 ;Perform addition
NC, L0
w2
L1
w2
SR, #C
Address Modifications
CHECK CARRY BIT BEFORE
DAW.b
DAW.b
;First BCD number
;Second BCD number
;If C set go to L0
;If not,do DAW and
;set the carry bit
;and exit
Instruction
3. Module: DISI Instruction
4. Module: Output Compare in PWM Mode
When a user executes a DISI #7, for example,
this will disable interrupts for 7 + 1 cycles (7 + the
DISI instruction itself). In this case, the DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but
the DISI state machine does not properly re-
engage and continue to disable interrupts. At this
point, all interrupts are enabled. The next time the
suer code executes a DISI instruction, the feature
will act normally and block interrupts.
In summary, it is only when a DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
the second problem is that on the next cycle after
the glitch, the OC pin does not go high, or, in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
© 2006 Microchip Technology Inc.
CY
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