DSPIC30F6011A-20I/PT Microchip Technology, DSPIC30F6011A-20I/PT Datasheet - Page 2
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DSPIC30F6011A-20I/PT
Manufacturer Part Number
DSPIC30F6011A-20I/PT
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6011A-30IPT.pdf
(234 pages)
3.DSPIC30F6011A-30IPT.pdf
(8 pages)
4.DSPIC30F6011A-30IPT.pdf
(10 pages)
5.DSPIC30F6011A-30IPT.pdf
(6 pages)
6.DSPIC30F6011A-30IPT.pdf
(8 pages)
7.DSPIC30F6011A-30IPT.pdf
(16 pages)
8.DSPIC30F6011A-20IPT.pdf
(238 pages)
Specifications of DSPIC30F6011A-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F6011A20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011A-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F6011A/6012A/6013A/6014A
10. PLL Lock Status Bit
11. PSV Operations
The following sections describe the errata and work
around to these errata, where they may apply.
DS80401A-page 2
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
1. Module: CPU –
EXAMPLE 1:
2. Module: Output Compare in PWM Mode
L0:daw.b
L1: ....
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the state of the Carry bit prior to executing
the DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b
instruction. Example 1 shows how the application
should process the Carry bit during a BCD addition
operation.
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
Additionally, on the next cycle after the glitch, the
OC pin does not go high, or, in other words, it
misses the next compare for any value written on
OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
.include “p30fxxxx.inc”
.......
mov.b
mov.b
add.b
bra
daw.b
bset.b
bra
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
#0x80, w0
#0x80, w1
w0, w1, w2 ;Perform addition
NC, L0
w2
L1
w2
SR, #C
DAW.b
CHECK CARRY BIT BEFORE
DAW.b
© 2008 Microchip Technology Inc.
;First BCD number
;Second BCD number
;If C set go to L0
;If not,do DAW and
;set the carry bit
;and exit
Instruction
CY
.