AT91SAM7S256-AU-001 Atmel, AT91SAM7S256-AU-001 Datasheet - Page 38

• Manufacturer Part Number: AT91SAM7S256-AU-001
• Description: IC ARM7 MCU 32BIT 256K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256-AU-001

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: AT91SAM7S256AU001

10.5
10.6
10.7
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Serial Peripheral Interface
Two-wire Interface
USART
AT91SAM7S Series Summary
• Supports communication with external serial devices
• Master or slave serial peripheral bus interface
• Master Mode only (AT91SAM7S512/256/128/64/321/32)
• Master, Multi-Master and Slave Mode support (AT91SAM7S161/16)
• General Call supported in Slave Mode (AT91SAM7S161/16)
• Compatibility with
• One, two or three bytes internal address registers for easy Serial Memory access
• 7-bit or 10-bit slave addressing
• Sequential read/write operations
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
• RS485 with driver control signal
– Four chip selects with external decoder allow communication with up to 15
– Serial memories, such as DataFlash
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Maximum frequency at up to Master Clock
– 1, 1.5 or 2 stop bits in Asynchronous Mode
– 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB or LSB first
– Optional break generation and detection
– By 8 or by 16 over-sampling receiver frequency
– Hardware handshaking RTS - CTS
– Modem Signals Management DTR-DSR-DCD-RI on USART1 (not present on
– Receiver time-out and transmitter timeguard
– Multi-drop Mode with address generation and detection
peripherals
Sensors
and data per chip select
AT91SAM7S32/16)
I
2
C
compatible devices (refer to the TWI sections of the datasheet)
®
and 3-wire EEPROMs
6175FS–ATARM–03-Dec-07