TS80C32X2-VCC Atmel, TS80C32X2-VCC Datasheet - Page 8

• Manufacturer Part Number: TS80C32X2-VCC
• Description: IC MCU 8BIT 40/20MHZ 44-PQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C32X2-VCC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60/30MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TS80C52X2
Enhanced Features
X2 Feature
Description
8
TS8xCx2X2
In comparison to the original 80C52, the TS80C52X2 implements some new features,
which are
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The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
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In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1
The X2 option
The Dual Data Pointer
The 4 level interrupt priority system
The power-off flag
The ONCE mode
The ALE disabling
Some enhanced features are also located in the UART and the Timer 2
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power
Save power consumption while keeping same CPU power (oscillator power saving)
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes
Increase CPU power by 2 while keeping same crystal frequency
:
F
XTAL
2
XTAL1:2
CKCON reg
X2
0
1
F
OSC
CPU control
state machine: 6 clock cycles.
4184G–8051–09/06