ATTINY26-16MJ Atmel, ATTINY26-16MJ Datasheet - Page 96
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ATTINY26-16MJ
Manufacturer Part Number
ATTINY26-16MJ
Description
ID MCU AVR 2K 5V 16MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Prescaling and
Conversion
Timing
96
ATtiny26(L)
stage will saturate at 0V (GND). This amplified value then becomes the analog input to the ADC.
If single ended channels are used, the gain amplifier is bypassed altogether.
The ADC can operate in two modes – Single Conversion and Free Running mode. In Single
Conversion mode, each conversion will have to be initiated by the user. In Free Running mode,
the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR
selects between the two available modes.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit
stays high as long as the conversion is in progress and will be set to zero by hardware when the
conversion is completed. If a different data channel is selected while a conversion is in progress,
the ADC will finish the current conversion before performing the channel change.
The ADC generates a 10-bit result, which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data
registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is
blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
Figure 52. ADC Prescaler
The successive approximation circuitry requires an input clock frequency between 50 kHz and
200 kHz. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can
be as high as 1000 kHz to get a higher sample rate.
ADEN
ADPS0
ADPS1
ADPS2
CK
Reset
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
1477K–AVR–08/10
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