ATMEGA16L-8PJ Atmel, ATMEGA16L-8PJ Datasheet - Page 98
![IC MCU AVR 16K 5V 8MHZ 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA16L-8PJ
Manufacturer Part Number
ATMEGA16L-8PJ
Description
IC MCU AVR 16K 5V 8MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16L-8PJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 98 of 357
- Download datasheet (8Mb)
Output Compare
Units
2466T–AVR–07/10
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-
pare Flag generates an output compare interrupt. The OCF1x Flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation
A special feature of output compare unit A allows it to define the Timer/Counter TOP value (that
is, counter resolution). In addition to the counter resolution, the TOP value defines the period
time for waveforms generated by the Waveform Generator.
Figure 43
names indicates the device number (n = 1 for Timer/Counter1), and the “x” indicates output com-
pare unit (A/B). The elements of the block diagram that are not directly a part of the output
compare unit are gray shaded.
Figure 43. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare
Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte
shows a block diagram of the output compare unit. The small “n” in the register and bit
OCRnxH Buf. (8-bit)
OCRnxH (8-bit)
BOTTOM
OCRnx Buffer (16-bit Register)
TEMP (8-bit)
TOP
OCRnx (16-bit Register)
(See “Modes of Operation” on page
OCRnxL Buf. (8-bit)
OCRnxL (8-bit)
DATA BUS
WGMn3:0
Waveform Generator
=
(16-bit Comparator )
(8-bit)
COMnx1:0
TCNTnH (8-bit)
OCFnx (Int.Req.)
101.)
TCNTn (16-bit Counter)
ATmega16(L)
TCNTnL (8-bit)
OCnx
98
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