ATMEGA162-16MJ Atmel, ATMEGA162-16MJ Datasheet - Page 139
![IC MCU AVR 16K 5V 16MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA162-16MJ
Manufacturer Part Number
ATMEGA162-16MJ
Description
IC MCU AVR 16K 5V 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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Definitions
Timer/Counter
Clock Sources
2513K–AVR–07/09
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-
tive when no clock source is selected. The output from the clock select logic is referred to as the
Timer Clock (clk
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC2).
Unit” on page 140.
which can be used to generate an output compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used i.e., TCNT2 for accessing Timer/Counter2
counter value and so on.
The definitions in
Table 59. Definitions
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
chronous Status Register – ASSR” on page
“Timer/Counter Prescaler” on page
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The
assignment is dependent on the mode of operation.
T
2).
Table 59
for details. The Compare Match event will also set the Compare Flag (OCF2)
are also used extensively throughout the section.
T
2 is by default equal to the MCU clock, clk
156.
152. For details on clock sources and prescaler, see
ATmega162/V
See “Output Compare
I/O
. When the AS2
“Asyn-
139
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