ATMEGA128L-8AJ Atmel, ATMEGA128L-8AJ Datasheet - Page 158
![IC MCU AVR 128K 8MHZ LV 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128L-8AJ
Manufacturer Part Number
ATMEGA128L-8AJ
Description
IC MCU AVR 128K 8MHZ LV 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128L-8AJ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Timer/Counter
Register – TCNT2
Output Compare
Register – OCR2
Timer/Counter
Interrupt Mask
Register – TIMSK
158
ATmega128
Table 68. Clock Select Bit Description
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2 Register.
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC2 pin.
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CS22
1
1
1
1
CS21
0
0
1
1
OCIE2
R/W
R/W
R/W
7
0
7
0
7
0
CS20
0
1
0
1
TOIE2
R/W
R/W
R/W
6
0
6
0
6
0
Description
clk
clk
External clock source on T2 pin. Clock on falling edge
External clock source on T2 pin. Clock on rising edge
TICIE1
R/W
R/W
I/O
I/O
R/W
5
0
5
0
5
0
/256 (From prescaler)
/1024 (From prescaler)
OCIE1A
R/W
R/W
R/W
4
0
4
0
4
0
TCNT2[7:0]
OCR2[7:0]
OCIE1B
R/W
R/W
R/W
3
0
3
0
3
0
TOIE1
R/W
R/W
R/W
2
0
2
0
2
0
OCIE0
R/W
R/W
R/W
1
0
1
0
1
0
TOIE0
R/W
R/W
R/W
0
0
0
0
0
0
TCNT2
OCR2
TIMSK
2467V–AVR–02/11
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