T89C51CC02UA-SISIM Atmel, T89C51CC02UA-SISIM Datasheet - Page 127
T89C51CC02UA-SISIM
Manufacturer Part Number
T89C51CC02UA-SISIM
Description
IC 8051 MCU FLASH 16K 28PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC02CA-TDSIM.pdf
(159 pages)
2.T89C51CC02CA-TDSIM.pdf
(33 pages)
3.T89C51CC02CA-TDSIM.pdf
(29 pages)
4.T89C51CC02CA-TDSIM.pdf
(148 pages)
Specifications of T89C51CC02UA-SISIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-PLCC
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC02UASISIM
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Figure 52. ADC Description
Figure 53. Timing Diagram
Note:
ADC Converter
Operation
4126L–CAN–01/08
Tsetup min, see the AC Parameter for A/D conversion.
Tconv = 11 clock ADC = 1sample and hold + 10-bit conversion
The user must ensure that Tsetup time between setting ADEN and the start of the first conversion.
AN0/P1.0
AN1/P1.1
AN2/P1.2
AN3/P1.3
AN4/P1.4
AN5/P1.5
AN6/P1.6
AN7/P1.7
ADEOC
ADSST
ADEN
CLOCK
CLK
ADC
ADCON.2
SCH2
000
001
010
011
100
101
110
111
T
SETUP
ADCON.1
SCH1
Figure 53 shows the timing diagram of a complete conversion. For simplicity, the figure
depicts the waveforms in idealized form and do not provide precise timing information.
For ADC characteristics and timing parameters refer to the section “AC Characteristics”
of this datasheet.
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is
set, an interrupt occur when flag ADEOC is set (See Figure 55). Clear this flag for re-
arming the interrupt.
Note:
ADCON.5
Sample and Hold
ADEN
CONTROL
ADCON.0
SCH0
Always leave Tsetup time before starting a conversion unless ADEN is permanently
high. In this case one should wait Tsetup only before the first conversion
Rai
Cai
ADCON.3
ADSST
AVSS
ADCIN
+
-
T
CONV
VAREF
ADEOC
ADCON.4
R/2R DAC
VAGND
SAR
EADC
IEN1.1
10
AT/T89C51CC02
8
2
ADDH
ADDL
ADC
Interrupt
Request
127
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