AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 95

• Manufacturer Part Number: AT89C5131-S3SIL
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131-S3SIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Registers
Serial Peripheral Control
Register (SPCON)
4136B–USB–09/03
Figure 45. SPI Interrupt Requests Generation
There are three registers in the module that provide control, status and data storage
functions. These registers are describes in the following paragraphs.
•
Table 75 describes this register and explains the use of each bit.
Table 75. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
Number
SPR2
Bit
The Serial Peripheral Control Register does the following:
–
–
–
–
–
7
6
5
5
4
3
7
Selects one of the Master clock rates
Configure the SPI module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI module
Frees the SS pin for a general-purpose
Bit Mnemonic Description
SPIF
MODF
SSDIS
SPEN
SSDIS
MSTR
CPHA
SPR2
SPEN
CPOL
6
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit has
no effect if CPHA = “0”.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to “0” in idle state.
Set to have the SCK set to “1” in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see CPOL).
SSDIS
5
SPI Transmitter
CPU Interrupt Request
SPI Receiver/Error
CPU Interrupt Request
MSTR
4
CPOL
3
CPHA
CPU Interrupt Request
2
SPI
AT89C5131
SPR1
1
SPR0
0
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