PIC18F2515-E/SO Microchip Technology, PIC18F2515-E/SO Datasheet - Page 188
PIC18F2515-E/SO
Manufacturer Part Number
PIC18F2515-E/SO
Description
IC MCU FLASH 24KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18LF2410-ISO.pdf
(376 pages)
3.PIC18LF2410-ISO.pdf
(8 pages)
4.PIC18F2515-ISO.pdf
(16 pages)
5.PIC18F2515-ISO.pdf
(6 pages)
6.PIC18F2515-ISO.pdf
(8 pages)
Specifications of PIC18F2515-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC18F2221-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18F2515-ISO PDF datasheet #4
- PIC18F2515-ISO PDF datasheet #5
- PIC18F2515-ISO PDF datasheet #6
- Current page: 188 of 376
- Download datasheet (7Mb)
PIC18F2X1X/4X1X
16.4.17.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 16-29:
FIGURE 16-30:
DS39636D-page 190
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
masters can assert SDA at exactly the same time.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 16-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 16-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
T
Cleared in software
© 2009 Microchip Technology Inc.
BRG
Interrupt cleared
in software
‘0’
‘0’
‘0’
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