PIC18F8525-E/PT Microchip Technology, PIC18F8525-E/PT Datasheet - Page 228
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F8525-E/PT
Manufacturer Part Number
PIC18F8525-E/PT
Description
IC PIC MCU FLASH 24KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F8525-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8525-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 228 of 396
- Download datasheet (8Mb)
PIC18F6525/6621/8525/8621
19.2.5
The Enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break
character transmit consists of a Start bit, followed by
twelve ‘0’ bits and a Stop bit. The frame Break charac-
ter is sent whenever the SENDB and TXEN bits
(TXSTAx<3> and TXSTAx<5>) are set while the
Transmit Shift register is loaded with data. Note that the
value of data written to TXREGx will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREGx for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 19-9 for the timing of the Break
character sequence.
19.2.5.1
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
FIGURE 19-9:
DS39612B-page 226
Reg. Empty Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREGx
(Transmit Buffer
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
TRMT bit
TXx (pin)
TXxIF bit
SENDB
BREAK CHARACTER SEQUENCE
Break and Sync Transmit Sequence
SEND BREAK CHARACTER SEQUENCE
Dummy Write
SENDB sampled here
Start Bit
Bit 0
Bit 1
Break
1.
2.
3.
4.
5.
When the TXREGx becomes empty, as indicated by
the TXxIF, the next data byte can be written to
TXREGx.
19.2.6
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the Auto-Wake-up feature
described in Section 19.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RXx/
DTx, cause an RCxIF interrupt and receive the next
data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXxIF interrupt is observed.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to set up the
Break character.
Load the TXREGx with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREGx to load the Sync
character into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
RECEIVING A BREAK CHARACTER
Bit 11
Auto-Cleared
2005 Microchip Technology Inc.
Stop Bit
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