PIC18F4439-E/ML Microchip Technology, PIC18F4439-E/ML Datasheet - Page 69
![IC PIC MCU FLASH 6KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4439-E/ML
Manufacturer Part Number
PIC18F4439-E/ML
Description
IC PIC MCU FLASH 6KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
12KB (6K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 69 of 322
- Download datasheet (7Mb)
7.0
7.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX39 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 7-1:
2002 Microchip Technology Inc.
16 x 16 unsigned
algorithms
8 x 8 unsigned
16 x 16 signed
8 x 8 signed
Routine
8 X 8 HARDWARE MULTIPLIER
Introduction
PERFORMANCE COMPARISON
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
Preliminary
Program
Memory
(Words)
13
33
21
28
52
35
1
6
7.2
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
EXAMPLE 7-2:
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
MOVF
MULWF
Cycles
(Max)
242
254
69
91
28
40
1
6
Operation
ARG1, W
ARG2
ARG1,
ARG2,
ARG2
ARG2,
PRODH, F
ARG1,
PRODH, F
@ 40 MHz
24.2 µs
25.4 µs
100 ns
600 ns
6.9 µs
9.1 µs
2.8 µs
4.0 µs
W
SB
W
SB
PIC18FXX39
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
;
; ARG1 * ARG2 ->
; PRODH:PRODL
@ 10 MHz
102.6 µs
27.6 µs
36.4 µs
96.8 µs
11.2 µs
16.0 µs
Time
400 ns
2.4 µs
DS30485A-page 67
- ARG1
- ARG2
@ 4 MHz
242 µs
254 µs
69 µs
91 µs
28 µs
40 µs
1 µs
6 µs
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