PIC18F442-E/ML Microchip Technology, PIC18F442-E/ML Datasheet - Page 3
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PIC18F442-E/ML
Manufacturer Part Number
PIC18F442-E/ML
Description
IC MCU FLASH 8KX16 EE A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.3
The code memory space extends from 0000h to 7FFFh
(32 Kbytes) in four, 8-Kbyte panels. Addresses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Panel 1. All code
memory is on-chip.
In addition to the code memory space, there are three
blocks in the configuration and ID space that are acces-
sible to the user through Table Reads and Table Writes.
Their locations in the memory map are shown in
Figure 2-3.
FIGURE 2-2:
2010 Microchip Technology Inc.
Unimplemented
Unimplemented
Unimplemented
Memory Map
(PIC18FX42)
Boot Block
16 Kbytes
Read ‘0’s
Read ‘0’s
Read ‘0’s
Block 0
Block 1
MEMORY SIZE / DEVICE
CODE MEMORY SPACE FOR PIC18FXX2/XX8 DEVICES
Unimplemented
(PIC18FX52)
32 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
000000h
0001FFh
000200h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
1FFFFFh
Address
Range
TABLE 2-2:
PIC18F242
PIC18F248
PIC18F252
PIC18F258
PIC18F442
PIC18F448
PIC18F452
PIC18F458
(Unimplemented Memory Space)
Device
Block Code Protection
PIC18FXX2/XX8
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
IMPLEMENTATION OF CODE
MEMORY
0000h - 3FFFh (16K)
0000h - 7FFFh (32K)
0000h - 3FFFh (16K)
0000h - 7FFFh (32K)
Code Memory Size
(Bytes)
DS39576C-page 3