PIC16LF87T-I/ML Microchip Technology, PIC16LF87T-I/ML Datasheet - Page 190
![IC MCU FLASH 4KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF87T-I/ML
Manufacturer Part Number
PIC16LF87T-I/ML
Description
IC MCU FLASH 4KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F87-IP.pdf
(228 pages)
4.PIC16F87-IP.pdf
(8 pages)
5.PIC16F87-IP.pdf
(4 pages)
6.PIC16F87-IP.pdf
(8 pages)
Specifications of PIC16LF87T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F87-IP PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- Current page: 190 of 228
- Download datasheet (5Mb)
PIC16F87/88
TABLE 18-10: I
DS30487C-page 188
100*
101*
102*
103*
90*
91*
106*
107*
92*
109*
110*
Note 1:
Param.
No.
2:
*
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
the requirement, T
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line, T
Standard mode I
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
:
:
:
:
:
STA
DAT
STO
STA
DAT
2
C™ BUS DATA REQUIREMENTS
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition
Setup Time
Start Condition Hold
Time
Data Input Hold
Time
Data Input Setup
Time
Stop Condition
Setup Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
2
C bus specification), before the SCL line is released.
SU
:
DAT
Characteristic
2
C™ bus device can be used in a Standard mode (100 kHz) I
250 ns, must then be met. This will automatically be the case if the device does
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
R
max. + T
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
SU
:
DAT
B
B
1000
3500
Max
300
300
300
= 1000 + 250 = 1250 ns (according to the
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
2005 Microchip Technology Inc.
C
10-400 pF
C
10-400 pF
Only relevant for
Repeated Start
condition
After this period, the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
2
C bus system, but
Conditions
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