ATMEGA162V-1PC Atmel, ATMEGA162V-1PC Datasheet - Page 142

• Manufacturer Part Number: ATMEGA162V-1PC
• Description: IC MCU AVR 16K 1.8V 8MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-1PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Clear Timer on Compare
Match (CTC) Mode
142
ATmega162(V/U/L)
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the
counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the
counter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 63. The counter value
(TCNT2) increases until a compare match occurs between TCNT2 and OCR2, and then
counter (TCNT2) is cleared.
Figure 63. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used
for updating the TOP value. However, changing the TOP to a value close to BOTTOM
when the counter is running with none or a low prescaler value must be done with care
since the CTC mode does not have the double buffering feature. If the new value written
to OCR2 is lower than the current value of TCNT2, the counter will miss the compare
match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its
logical level on each compare match by setting the Compare Output mode bits to toggle
mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data
direction for the pin is set to output. The waveform generated will have a maximum fre-
quency of f
defined by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the
that the counter counts from MAX to 0x00.
TCNTn
OCn
(Toggle)
Period
OC
2 = f
clk_I/O
1
/2 when OCR2 is set to zero (0x00). The waveform frequency is
f
OCn
2
=
---------------------------------------------- -
2 N
TOV2
f
3
clk_I/O
1
+
flag is set in the same timer clock cycle
OCRn
4
OCn Interrupt Flag Set
(COMn1:0 = 1)
2513C–AVR–09/02