ATMEGA162-16MC Atmel, ATMEGA162-16MC Datasheet - Page 102

• Manufacturer Part Number: ATMEGA162-16MC
• Description: IC MCU AVR 16K 5V 16MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Timer/Counter0,
Timer/Counter1, and
Timer/Counter3
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
102
ATmega162(V/U/L)
Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler mod-
ule, but the Timer/Counters can have different prescaler settings. The description below
applies to Timer/Counter3, Timer/Counter1, and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
caler can be used as a clock source. The prescaled clock has a frequency of either
f
option of choosing f
The prescaler is free running, i.e., operates independently of the clock select logic of the
Timer /Counter , and it is shar ed by Ti mer/Co unter 3, Timer /Counter 1, a nd
Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock select,
the state of the prescaler will have implications for situations where a prescaled clock is
used. One example of prescaling artifacts occurs when the Timer is enabled and
clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from
when the Timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024, additional selections
for Timer/Counter3: 32 and 64).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also uses prescaling. A Prescaler Reset will affect the prescaler period
for all Timer/Counters it is connected to.
An external clock source applied to the Tn/T0 pin can be used as Timer/Counter clock
(clk
every system clock cycle by the pin synchronization logic. The synchronized (sampled)
signal is then passed through the edge detector. Figure 44 shows a functional equiva-
lent block diagram of the Tn/T0 synchronization and edge detector logic. The registers
are clocked at the positive edge of the internal system clock (
parent in the high period of the internal system clock.
The edge detector generates one clk
ative (CSn2:0 = 6) edge it detects.
Figure 44. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the Tn/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn/T0 has been stable for
at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock
pulse is generated.
CLK_I/O
Tn
clk
T1
I/O
/clk
/8, f
T
0) for Timer/Counter1 and Timer/Counter0. The Tn/T0 pin is sampled once
CLK_I/O
D
LE
/64, f
Q
CLK_I/O
Synchronization
CLK_I/O
D
/16 and f
Q
/256, or f
CLK_I/O
CLK_I/O
T1
CLK_I/O
/clk
/32.
). Alternatively, one of four taps from the pres-
T
0
/1024. In addition, Timer/Counter3 has the
pulse for each positive (CSn2:0 = 7) or neg-
D
Q
clk
I/O
). The latch is trans-
Edge Detector
2513C–AVR–09/02
Tn_sync
(To Clock
Select Logic)