AT90LS8535-4MC Atmel, AT90LS8535-4MC Datasheet
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AT90LS8535-4MC
Manufacturer Part Number
AT90LS8535-4MC
Description
IC MCU 8K FLASH 4MHZ COM 44-QFN
Manufacturer
Atmel
Series
AVR® 90LSr
Specifications of AT90LS8535-4MC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Errata (All Date Codes)
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10. Releasing Reset Condition without Clock
9. Incorrect Channel Changes in Free Running Mode
8. 32 kHz Oscillator may Fail at Higher Voltages
7. Error in Half Carry Flag
Releasing Reset Condition without Clock
Incorrect Channel Changes in Free Running Mode
32 kHz Oscillator may Fail at Higher Voltages
Error in Half Carry Flag
Error in Writing Reset Status Bits
Wake-up from Sleep Executes Instructions before the Interrupt is Serviced
The SPI Can Send Wrong Byte
Serial Programming at Voltages below 3.0V
Wake-up from Power-save without Global Interrupt Enabled
UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled
If an external reset or a watchdog reset occurs while the clock is stopped and
reset is released before the clock is restarted, the internal reset will timeout after
the start-up delay which is independent of the external clock. If no external clock
pulses are present in the period when internal reset is active, the reset does cor-
rectly cause tri-stating of the I/O while the reset is held. However, if the internal
reset is released before the clock starts running, the part does not clear I/O regis-
ters, nor sets PC to 0x00. Here, stopping the clock refers to gating the external
clock input. Power-down or Power-save mode do not have this issue.
Problem Fix/Workaround
Make sure the clock is running whenever an external reset can be expected. If the
Watchdog is used, never stop an external clock.
If the ADC operates in Free Running Mode and channels are changed by writing
to ADMUX shortly after the ADC Interrupt Flag (ADIF in ADCSR) is set, the new
setting in ADMUX may affect the ongoing conversion.
Problem Fix/Workaround
Use Single Conversion Mode when scanning channels, or avoid changing
ADMUX until at least 0.5 ADC clock cycles after ADIF goes high.
When using an external 32 kHz crystal as asynchronous clock source for Timer2,
the timer may count incorrectly at voltages above 4.0V.
Problem Fix/Workaround
Keep the supply voltage below 4.0V when clocking Timer2 from an external
crystal.
The half carry flag is undefined after executing the commands “ror”, “asr” and “lsr”.
Problem Fix/Workaround
Do not use the half carry flag value after executing the above instructions.
8-bit
Microcontroller
with 8K Bytes of
In-System
Programmable
Flash
AT90S/LS8535
Rev. E
Errata Sheet
Rev. 1657C–11/01
1
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AT90LS8535-4MC Summary of contents
Page 1
Errata (All Date Codes) • Releasing Reset Condition without Clock • Incorrect Channel Changes in Free Running Mode • 32 kHz Oscillator may Fail at Higher Voltages • Error in Half Carry Flag • Error in Writing Reset Status Bits ...
Page 2
Error in Writing Reset Status Bits The EXTRF flag in MCUSR will be cleared when clearing the PORF-flag. The flag does not get cleared by writing a “0” to it. Problem Fix/Workaround Finish the test of both flags before ...
Page 3
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