PIC18F452-I/LG Microchip Technology, PIC18F452-I/LG Datasheet - Page 151
PIC18F452-I/LG
Manufacturer Part Number
PIC18F452-I/LG
Description
IC MCU FLASH 16KX16 W/AD 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F452-I/LG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
For Use With
XLT44L2 - SOCKET TRAN ICE 44PLCCDVA16XL441 - ADAPTER DEVICE ICE 44PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 151 of 332
- Download datasheet (6Mb)
15.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I
P bit is set or the bus is IDLE, with both the S and P bits
clear.
In Firmware Controlled Master mode, user code con-
ducts all I
STOP bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 15-16:
© 2006 Microchip Technology Inc.
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a STOP condition on SDA and SCL.
SDA
SCL
2
MASTER MODE
C bus operations based on START and
to
the
2
C port to receive data.
SSPBUF
MSSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA in
Bus Collision
SCL in
register
Read
initiating
MSb
START bit, STOP bit,
Write Collision Detect
end of XMIT/RCV
START bit Detect
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
Generate
SSPSR
2
C MASTER MODE)
LSb
Write
The following events will cause SSP interrupt flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START
Clock
Data Bus
Shift
Note:
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
The MSSP Module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
PIC18FXX2
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS39564C-page 149
2
C
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