ATTINY26-16SC Atmel, ATTINY26-16SC Datasheet - Page 121
![IC AVR MCU 2K 16MHZ COM 20-SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY26-16SC
Manufacturer Part Number
ATTINY26-16SC
Description
IC AVR MCU 2K 16MHZ COM 20-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26-16SC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY26-16SC
Manufacturer:
MITEL
Quantity:
20 000
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Serial
Downloading
Serial
Programming Pin
Mapping
1477K–AVR–08/10
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 59 on page 121, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO
are used to describe the serial data in and serial data out respectively.
Table 59. Pin Mapping Serial Programming
Figure 67. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-
tion. The Chip Erase operation turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
1. If the device is clocked by the internal oscillator, there is no need to connect a clock source to
2. V
Symbol
the XTAL1 pin.
MOSI
MISO
SCK
CC
-0.3V < AVCC < V
MOSI
MISO
SCK
CC
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Pins
+0.3V, however, AVCC should always be within 2.7 - 5.5V.
PB0
PB1
PB2
PB0
PB1
PB2
XTAL1
RESET
GND
(1)
I/O
O
I
I
AVCC
Description
Serial data in
Serial data out
Serial clock
VCC
2.7 - 5.5V
2.7 - 5.5V
ck
ck
(2)
12 MHz
12 MHz
121
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