ATMEGA32L-8MC Atmel, ATMEGA32L-8MC Datasheet - Page 122
ATMEGA32L-8MC
Manufacturer Part Number
ATMEGA32L-8MC
Description
IC AVR MCU 32K LV 8MHZ COM 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32L-8MC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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2503Q–AVR–02/11
Figure 59. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out-
put can be generated by setting the COM21:0 to 3 (see
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2 Register at the compare match
between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2
Register at compare match between OCR2 and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
THere are two cases that give a transition without Compare Match.
•
•
OCR2A chages its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
OCn
OCn
Period
Figure 59
1
TOV2
f
OCnPCPWM
OCn has a transition from high to low even though there
) is set each time the counter reaches BOTTOM. The
2
Figure
=
----------------- -
N 510
f
clk_I/O
⋅
59. When the OCR2A value is MAX the
Table 53 on page
3
ATmega32(L)
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
(COMn1:0 = 2)
(COMn1:0 = 3)
126). The actual OC2
122
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