ATMEGA16-16PC Atmel, ATMEGA16-16PC Datasheet - Page 144

IC AVR MCU 16K 16MHZ COM 40-DIP

ATMEGA16-16PC

Manufacturer Part Number
ATMEGA16-16PC
Description
IC AVR MCU 16K 16MHZ COM 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16-16PC

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16-16PC
Manufacturer:
ATM
Quantity:
100
USART
Overview
2466T–AVR–07/10
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
A simplified block diagram of the USART transmitter is shown in
Registers and I/O pins are shown in bold.
Figure 69. USART Block Diagram
Note:
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
1. Refer to
placement.
Figure 1 on page
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
UDR (Receive)
UBRR[H:L]
(1)
2,
Table 33 on page
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
65, and
DATA
OSC
Table 27 on page 60
Figure
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
ATmega16(L)
Transmitter
PIN
PIN
PIN
69. CPU accessible I/O
RX
TX
Receiver
UCSRC
for USART pin
XCK
RxD
TxD
144

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