T89C51CC02UA-SITIM Atmel, T89C51CC02UA-SITIM Datasheet - Page 2

• Manufacturer Part Number: T89C51CC02UA-SITIM
• Description: IC 8051 MCU FLASH 16K 28PLCC
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of T89C51CC02UA-SITIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-PLCC
• For Use With: AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C51CC02UASITIM

5. Timer 2 (Baud Rate Generator Mode) – Long Start Time
6. UART - RB8 Lost With JBC on SCON Register
7. CAN – CANCONCH Harmless Corruption
8. ADC - Interrupt Controller/ADC Idle Mode/Loops In High Priority Interrupt
9. Flash/EEPROM – First Read After Load Disturbed
2
When Timer 2 is used as baud rate generator, TH2 is not loaded with RACP2H at the beginning, then UART is not
operational before almost 10,000 machine cycles.
Workaround
In the software add an initialization of TH2 and TL2, with the value of RCAP2H and RCAP2L.
When using the JBC instruction on any bit of SCON register, if RB8 changes from 1 to 0, the 0 bit can be lost.
Workaround
After each use clear RB8.
When a stuff error occurs during a CAN frame transmission on DPRAM write access, the CONCH1, CONCH0 bits in
CANCONCH are corrupted. This corruption has no effect on the correct behavior of the Transmit channel.
Workaround
No workaround required, re-writing CANCONCH to start a new message takes care of the corruption.
The problem occurs during an A/D conversion in idle mode, if a hardware re-setable interrupt occurs followed by a sec-
ond interrupt with higher priority before the end of the A/D conversion. If the above configuration occurs, the high
priority interrupt is served immediately after the A/D conversion. At the end of the high priority interrupt service, the pro-
cessor will not serve the hardware resetable interrupt pending. It will also not serve any new interrupt requests with a
priority lower than the high level priority last served.
Workaround
Disable all interrupts (Interrupt Global Interrupt Bit) before starting an A/D conversion in idle mode, then re-enable all
interrupts immediately after.
In the "In-Application Programming" mode from the Flash, if the User software application load the Column Latch Area
prior to call the programming sequence in the CAN Bootloader.
The "Read after load" issue leads to a wrong Opcode Fetch during the column latch load sequence.
Workaround
Either:
- Update of the Flash API Library. A NOP instruction has to be inserted after the load instruction.
or :
- Use the Flash API which load the column latch from bootloader (refer to datasheet boot loader to see if this flash API
exist).
MOVX @DPTR,A ;Load Column latches
NOP ; ADDED INSTRUCTION
4160B–CAN–12/02