T89C51CC01UA-RLTIM Atmel, T89C51CC01UA-RLTIM Datasheet - Page 97
T89C51CC01UA-RLTIM
Manufacturer Part Number
T89C51CC01UA-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
2.T89C51CC01CA-7CTIM.pdf
(12 pages)
3.T89C51CC01CA-7CTIM.pdf
(32 pages)
4.T89C51CC01CA-7CTIM.pdf
(29 pages)
Specifications of T89C51CC01UA-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01UARLTIM
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4129N–CAN–03/08
Table 59. CANGSTA Register
CANGSTA (S:AAh Read Only)
CAN General Status Register
Reset Value = x0x0 0000b
Number
Bit
7
-
7
6
5
4
3
2
1
0
Bit Mnemonic Description
OVFG
OVFG
ENFG
ERRP
TBSY
RBSY
BOFF
6
-
-
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Overload Frame Flag
This status bit is set by the hardware as long as the produced overload frame
is sent.
This flag does not generate an interrupt
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Transmitter Busy
This status bit is set by the hardware as long as the CAN transmitter
generates a frame (remote, data, overload or error frame) or an ack field. This
bit is also active during an InterFrame Spacing if a frame must be sent.
This flag does not generate an interrupt.
Receiver Busy
This status bit is set by the hardware as long as the CAN receiver acquires or
monitors a frame.
This flag does not generate an interrupt.
Enable On-chip CAN Controller Flag
Because an enable/disable command is not effective immediately, this status
bit gives the true state of a chosen mode.
This flag does not generate an interrupt.
Bus Off Mode
see Figure 49
Error Passive Mode
see Figure 49
5
-
TBSY
4
RBSY
3
ENFG
2
BOFF
1
ERRP
0
97
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