PIC17C752-16E/PT Microchip Technology, PIC17C752-16E/PT Datasheet - Page 86
PIC17C752-16E/PT
Manufacturer Part Number
PIC17C752-16E/PT
Description
IC MCU CMOS 16MHZ 8K EPRM 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C752-16E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C752-16E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
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- Download datasheet (6Mb)
PIC17C7XX
10.7
PORTG is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRG. A ’1’ in
DDRG configures the corresponding port pin as an
input. A ’0’ in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG reads
the status of the pins, whereas writing to PORTG will
write to the port latch.
The lower four bits of PORTG are multiplexed with four
channels of the 10-bit A/D converter.
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
Upon RESET, RG3:RG0 is automatically configured as
analog inputs and must be configured in software to be
a digital I/O.
FIGURE 10-14:
DS30289B-page 86
WR PORTG
WR DDRG
RD PORTG
Note: I/O pins have protection diodes to V
V
Data Bus
AIN
PORTG and DDRG Registers
PCFG3:PCFG0
CHS3:CHS0
BLOCK DIAGRAM OF RG3:RG0
Data Latch
DDRG Latch
D
CK
D
CK
RD DDRG
Q
Q
Q
Q
DD
and V
SS
Q
.
EN
EN
D
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-7:
To other pads
To other pads
CLRF
MOVWF
MOVLB
MOVLW
MOVPF
MOVLW
PORTG, F
5
0x0E
WREG, ADCON1
DDRG
0x03
V
V
P
N
DD
SS
INITIALIZING PORTG
2000 Microchip Technology Inc.
; Initialize PORTG data
; Set RG<1:0> as inputs
;
;
; Select Bank 5
; Configure PORTG as
; digital
;
;
; Value used to init
;
the data direction
RG<7:2> as outputs
latches before
register
data direction
ST
Input
Buffer
I/O pin
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