PIC16F84AT-20E/SS Microchip Technology, PIC16F84AT-20E/SS Datasheet - Page 282
![IC MCU CMOS 20MHZ 1K FLSH 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F84AT-20E/SS
Manufacturer Part Number
PIC16F84AT-20E/SS
Description
IC MCU CMOS 20MHZ 1K FLSH 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84AT-20E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
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PICmicro MID-RANGE MCU FAMILY
Register 17-2:
DS31017A-page 17-6
bit 7
bit 6
bit 5
bit 4
SSPCON1: SSP Control Register1
bit 7
WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as the source of the
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I
Unused in this mode
WCOL
R/W-0
2
2
2
2
port pins
serial port pins
transmission to be started
(must be cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. In slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting over-
flow. In master mode the overflow bit is not set since each new reception (and transmission)
is initiated by writing to the SSPBUF register.
“don’t care” in transmit mode. SSPOV must be cleared in software in either mode. (must be
cleared in software)
C master mode
C mode:
C mode:
C slave mode:
SSPOV
R/W-0
SSPEN
R/W-0
Preliminary
R/W-0
CKP
SSPM3
R/W-0
2
C conditions were not valid for a
SSPM2
R/W-0
1997 Microchip Technology Inc.
SSPM1
R/W-0
bit 0
SSPM0
R/W-0
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