PIC18C442-E/L Microchip Technology, PIC18C442-E/L Datasheet - Page 2

• Manufacturer Part Number: PIC18C442-E/L
• Description: IC MCU OTP 8KX16 A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-PLCC
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C442E/L

MSSP MODULE
Clarifications/Corrections to the Data
Sheets
REGISTER 1:
DS80131E-page 2
Note:
Items 1-3 apply to the Data Sheets for the
following devices:
• PIC16C717/770/771 (DS41120B)
• PIC16C773/774 (DS30275A)
• PIC16F872 (DS30221B)
• PIC16F873/874/876/877 (DS30292C)
• PIC16F873A/874A/876A/877A
• PIC17C752/756A/762/766 (DS30289B)
• PIC18C242/252/442/452 (DS39026C)
• PIC18C601/801 (DS39541A)
• PIC18C658/858 (DS30475A)
• PIC18F242/252/442/452 (DS39564B)
• PIC18F2220/2320/4220/4320
• PIC18F2439/2539/4439/4539
• PIC18F6520/6620/6720/8520/8620/
• PIC18F6585/6680/8585/8680
bit 6
(DS39582B)
(DS39599C)
(DS30485A)
8720 (DS39609B)
(DS30491C)
SSPSTAT: MSSP STATUS REGISTER (EXCERPT)
CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
1. Module: MSSP (SPI Mode)
2. Module: MSSP (SPI Slave Mode)
The description of the operation of the CKE bit
(SSPSTAT<6>) is clarified. Please substitute the
description in Register 1, below, for all occurrences
of the existing text for the SSPSTAT register, bit 6
(new text in bold).
The description of the operation of SPI Slave
mode is clarified as follows: the state of the clock
line (SCK) must match the polarity for the Idle state
before enabling the module.
The subsection of the “MSSP Module” chapter,
entitled “Slave Mode” (Subsection 3.6 in the
majority of data sheets, Subsection 3.5 in others),
is amended by adding the following paragraph to
the end of the existing text:
“Before enabling the module in SPI Slave mode,
the clock line must match the proper Idle state.
The clock line can be observed by reading the
SCK pin. The Idle state is determined by the CKP
bit (SSPCON1<4>) .”
Note:
This text refers only to the operation of
the CKE bit in SPI mode; its operation
in I
data sheets that describe the SSPSTAT
register in separate locations for SPI
and I
only to the register titled “SSPSTAT
Register (SPI Mode)”.
2
C mode is unchanged. For those
2
C modes, this description applies
© 2006 Microchip Technology Inc.