PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 5

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

13. Module: I/O (PORTB
14. Module: Interrupts
 2003 Microchip Technology Inc.
The RB Port Change Flag bit of the INTCON reg-
ister (RBIF, INTCON<0>) may be inadvertently
cleared, even when the PORTB<7:4> pins have
not been read. This will occur only when the follow-
ing two conditions occur simultaneously:
•
•
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh. In addition
to those proposed below, other solutions may exist.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
When an interrupt occurs simultaneously with the
clearing of one or more interrupt enable flags in the
INTCON, PIE1 or PIE2 registers, the instruction
immediately following the interrupted instruction
may be executed before vectoring to the Interrupt
Service Routine (ISR). If that instruction is a con-
trol operation, the ISR may not execute as
intended.
In the case of conditional branch instructions, the
first instruction of the ISR may be skipped if the
tested condition would have resulted in a branch.
The four Least Significant bits of the
BSR register are equal to 0Fh
(BSR<3:0> = 1111), and
Any instruction that contains 81h in its
8 Least Significant bits (i.e., register file
addresses, literal data, address offsets,
etc.) is executed.
these guidelines in mind:
•
•
•
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instructions contain 81h in the 8 Least Signifi-
cant bits, while the BSR points to Bank 15
(BSR = 0Fh).
Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
Do not set the BSR to point to Bank 15
(BSR = 0Fh).
Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be
done through the Access Bank. Con-
tinue to use the BSR to select Banks 1
through 5, and the upper half of Bank 0.
Interrupt-on-Change)
15. Module: CAN Module
In the case of GOTO, CALL, or BRA instructions,
program execution may vector to the address
encoded in the instruction; the ISR will not be exe-
cuted at all. The GIE bit will still be cleared, dis-
abling all interrupts.
Additionally, on return from the interrupt (by exe-
cuting RETFIE), the instruction following the inter-
rupted instruction may be executed again.
There may be other interrupt related symptoms.
Work around
Three possible solutions are presented here.
Other solutions may exist. None of these require
special attention when setting interrupt enable bits.
1. All instructions that clear interrupt enable bits
2. Prior to disabling any interrupt source, disable
3. If interrupt priority is being used:
Under certain circumstances, the module may
transmit unexpected messages. This will only hap-
pen when all of the following conditions occur
simultaneously:
1. The identifier registers for Transmit buffer
2. Either of the transmit buffers, TXB1 or TXB2,
3. The CAN module attempts to retransmit a
Work around
Clear the TXB0SIDL and TXB0SIDH registers as
part of the CAN initialization routine.
should be followed by a NOP instruction.
all
(INTCON<7>). After disabling the desired inter-
rupts, re-enable all interrupts by setting GIE.
a) clear both GIEL and GIEH (in order) bits
b) clear the desired interrupt enable bits
c) set both GIEH and GIEL, in order to re-enable
TXB0 are never used or written to;
are in use; and
message that has lost one or more previous
arbitrations.
(INTCON<7:6>) to disable all peripheral
interrupts
peripheral interrupts
interrupts
PIC18C658/858
by
clearing
DS80084M-page 5
the
GIE
bit