AT91M55800-33CI Atmel, AT91M55800-33CI Datasheet - Page 13

• Manufacturer Part Number: AT91M55800-33CI
• Description: IC ARM7 MCU 176 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800-33CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT91M5580033CI

Master Clock
Reset
NRST Pin
Watchdog Reset
Emulation Functions
Tri-state Mode
JTAG/ICE Debug Mode
1745CS–ATARM–05/02
Master Clock is generated in one of the following ways, depending on programming in
the APMC registers:
•
•
The Master Clock (MCK) is also provided as an output of the device on the MCKO pin,
whose state is controlled by the APMC module.
Reset restores the default states of the user interface registers (defined in the user inter-
face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch
from address zero. Aside from the program counter, the ARM7TDMI registers do not
have defined reset states.
NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-
chronized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768
Hz crystal), and the signal presented on MCK must be active within the specification for
a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct
operation.
The watchdog can be programmed to generate an internal reset. In this case, the reset
has the same effect as the NRST pin assertion, but the BMS and NTRI pins are not
sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted
and the watchdog triggers the internal reset, the NRST pin has priority.
The AT91M55800A provides a Tri-state Mode, which is used for debug purposes. This
enables the connection of an emulator probe to an application board without having to
desolder the device from the target board. In Tri-state Mode, all the output pin drivers of
the AT91M55800A microcontroller are disabled.
To enter Tri-state Mode, the NTRI pin must be held low during the last 10 clock cycles
before the rising edge of NRST. For normal operation the NTRI pin must be held high
during reset, by a resistor of up to 400K Ohm.
NTRI is multiplexed with I/O line PA18 and USART 1 serial data transmit line TXD1.
Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1
is connected to a device not including this pull-up, the user must make sure that a high
level is tied on NTRI while NRST is asserted.
ARM Standard Embedded In-Circuit Emulation is supported via the JTAG/ICE port. It is
connected to a host computer via an external ICE Interface. The JTAG/ICE debug mode
is enabled when JTAGSEL is low.
In ICE Debug Mode the ARM Core responds with a non-JTAG chip ID which identifies
the core to the ICE system. This is not JTAG compliant.
From the 32768 Hz low-power oscillator that clocks the RTC
The on-chip main oscillator, together with a PLL, generate a software-programmable
main clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to
allow the user to enter an external clock signal.
AT91M55800A
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