AT89LV52-12PC Atmel, AT89LV52-12PC Datasheet - Page 10

• Manufacturer Part Number: AT89LV52-12PC
• Description: IC MICRO CTRL 12MHZ 40DIP
• Manufacturer: Atmel
• Series: 89LVr

Specifications of AT89LV52-12PC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: UART/USART
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Other names: AT89LV5212PC

Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu-
lar I/O pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 3
MHz at a 12 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
In the clock-out mode, Timer 2 roll-overs will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
UART
The UART in the AT89LV52 operates the same way as the
UART in the AT89LV51.
Interrupts
The AT89LV52 has a total of six interrupt vectors: two
external interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 6.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimple-
mented. In the AT89LV51, bit position IE.5 is also unimple-
mented. User software should not write 1s to these bit posi-
tions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
4-92
Clock Out Frequency
=
-----------------------------------------------------------------------------------------------
32
65536
Oscillator Frequency
–
RCAP2H,RCAP2L
Not
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Table 5. Interrupt Enable (IE) Register
Figure 6. Interrupt Sources
Symbol
User software should never write 1s to unimplemented bits,
because they may be used in future AT89 products.
ET2
ET1
EX1
ET0
EX0
EA
ES
—
(MSB)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
EA
EXF2
INT0
INT1
TF2
TF0
TF1
RI
TI
Position
—
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
ET2
0
1
0
1
Function
interrupt is acknowledged. If EA = 1,
each interrupt source is individually
enabled or disabled by setting or
clearing its enable bit.
Disables all interrupts. If EA = 0, no
Reserved.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
ES
ET1
EX1
IE0
IE1
ET0
(LSB)
EX0