AT89S53-24AC Atmel, AT89S53-24AC Datasheet
AT89S53-24AC
Specifications of AT89S53-24AC
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AT89S53-24AC Summary of contents
Page 1
... Flash, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Point- ers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S53 is designed with static logic for operation down to zero frequency and supports two soft- ware selectable power saving modes ...
Page 2
... Supply voltage. GND Ground. Port 0 Port 8-bit open drain bidirectional I/O port output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. AT89S53 2 33 P0.4 (AD4) 32 P0.5 (AD5) 31 P0.6 (AD6 ...
Page 3
... INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 3 DOG LATCH PORT 3 DRIVERS P3.0 - P3.7 P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR PORT 1 SPI PROGRAM LATCH PORT LOGIC PORT 1 DRIVERS P1.0 - P1.7 AT89S53 3 ...
Page 4
... PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT89S53 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...
Page 5
... FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V for internal program execu- CC tions. This pin also receives the 12-volt programming Table 1. AT89S53 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC ...
Page 6
... Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89S53 6 Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 9) for Timer 2 ...
Page 7
... Data Pointer register. Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET. AT89S53 Reset Value = 0000 0010B DPS WDTRST WDTEN ...
Page 8
... SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register. Table 6. SPDR—SPI Data Register SPDR Address = 86H SPD7 SPD6 Bit 7 6 AT89S53 8 DORD MSTR CPOL divided by – ...
Page 9
... Table 7. Watchdog Timer Period Selection Timer 0 and 1 Timer 0 and Timer 1 in the AT89S53 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.” ...
Page 10
... Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 AT89S53 10 current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set ...
Page 11
... Bit 7 6 Symbol Function – Not implemented, reserved for future use. T2OE Timer 2 Output Enable bit. DCEN When set, this bit allows Timer configured as an up/down counter. 0787E–MICRO–3/06 – – – AT89S53 Reset Value = XXXX XX00B – T2OE DCEN ...
Page 12
... Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) Figure 4. Timer 2 in Baud Rate Generator Mode NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ 2 OSC C/ C/ PIN TRANSITION DETECTOR T2EX PIN AT89S53 12 TH2 TL2 CONTROL TR2 RCAP2H RCAP2L EXF2 CONTROL EXEN2 TIMER 1 OVERFLOW ÷ 2 "0" ...
Page 13
... This behavior is similar to when Timer 2 is used as a baud-rate generator possible to use Timer baud-rate generator and a clock generator simulta- neously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. AT89S53 Oscillator Frequency = ------------------------------------------------------------------------------------------ - × [ ...
Page 14
... Figure 5. Timer 2 in Clock-Out Mode Figure 6. SPI Block Diagram OSCILLATOR DIVIDER ÷4÷16÷64÷128 SELECT SPI CONTROL SPI STATUS REGISTER AT89S53 14 MSB 8/16-BIT SHIFT REGISTER READ DATA BUFFER SPI CLOCK (MASTER) CLOCK LOGIC MSTR SPE 8 SPI CONTROL REGISTER 8 8 SPI INTERRUPT ...
Page 15
... UART The UART in the AT89S53 operates the same way as the UART in the AT89C51, AT89C52 and AT89C55. For fur- ther information, see the October 1995 Microcontroller Data Book, page 2-49, section titled, “Serial Interface.” Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed syn- chronous data transfer between the AT89S53 and peripheral devices or between several AT89S53 devices ...
Page 16
... SS (TO SLAVE) *Not defined but normally LSB of previously transmitted character Interrupts The AT89S53 has a total of six interrupt vectors: two exter- nal interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. ...
Page 17
... Figure 11. Oscillator Connections C1 ± for Crystals Note ± for Ceramic Resonators Figure 12. External Clock Drive Configuration AT89S53 17 ...
Page 18
... Float Program Memory Lock Bits The AT89S53 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value and holds that value until reset is activated ...
Page 19
... Set RST and EA pins to “L”. Turn V power off. CC Data Polling: The AT89S53 features DATA Polling to indi- cate the end of a write cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the last byte written will result in the complement of the writ- ten datum on P0 ...
Page 20
... With a 24 MHz oscillator clock, the maximum SCK frequency is 600 kHz. AT89S53 20 Serial Programming Algorithm To program and verify the AT89S53 in the serial program- ming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “H”. ...
Page 21
... Set LB1, LB2 or LB3 = “0” to program lock bits. RST PSEN ALE/PROG EA/V PP ( 12V H L 12V 12V H L 12V 12V 12V 12V ( 12V ( 12V 12V AT89S53 Data I/O P2.6 P2.7 P3.6 P3.7 P0.7 DIN DOUT DIN DOUT @P0.2 @P0.1 @P0 DOUT DOUT L H ...
Page 22
... AT89S53 22 Figure 15. Flash Serial Downloading + PGM P0 DATA INSTRUCTION ALE PROG DATA OUTPUT 3-24 Mhz RST PSEN + PGM DATA P0 (USE 10K PULLUPS) ALE RST I H PSEN +4.0V to 6.0V AT89S53 V CC P1.5/MOSI INPUT P1.6/MISO P1.7/SCK CLOCK IN XTAL2 XTAL1 RST GND 0787E–MICRO–3/06 ...
Page 23
... GLGH t Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float after ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC 0787E–MICRO–3/06 PP AT89S53 Min Max Units 11.5 12 MHz 48t CLCL 48t CLCL 48t CLCL ...
Page 24
... Flash Programming and Verification Waveforms – Parallel Mode Serial Downloading Waveforms SERIAL CLOCK INPUT SCK/P1.7 SERIAL DATA INPUT MOSI/P1.5 SERIAL DATA OUTPUT MISO/P1.6 AT89S53 MSB LSB LSB MSB 0787E–MICRO–3/06 ...
Page 25
... CC 0.45 < V < Test Freq MHz 25°C A Active Mode, 12 MHz Idle Mode, 12 MHz Maximum total related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum V AT89S53 Min Max -0.5 0 0.1 CC -0.5 0 0 0.5 0.5 2 ...
Page 26
... ALE Low Low LLWL t Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold after WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89S53 26 12MHz Oscillator Variable Oscillator Min Max Min 0 127 CLCL CLCL CLCL ...
Page 27
... External Program Memory Read Cycle External Data Memory Read Cycle 0787E–MICRO–3/06 AT89S53 27 ...
Page 28
... External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89S53 4.0V to 6.0V CC Min Max 0787E–MICRO–3/06 Units MHz ...
Page 29
... CLCL 2t - 117 CLCL 0 10t CLCL (1) 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V /V level occurs AT89S53 Units µ 133 ns 29 ...
Page 30
... Notes: AT89S53 30 1. XTAL1 tied to GND for I (power-down Lock bits programmed 0787E–MICRO–3/06 ...
Page 31
... Ordering Information Speed Power Ordering Code (MHz) Supply 24 4.0V to 6.0V AT89S53-24AC AT89S53-24JC AT89S53-24PC 4.0V to 6.0V AT89S53-24AI AT89S53-24JI AT89S53-24PI 33 4.5V to 5.5V AT89S53-33AC AT89S53-33JC AT89S53-33PC 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 0787E– ...
Page 32
... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S53 TITLE 44A, 44-lead Body Size, 1 ...
Page 33
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0787E–MICRO–3/06 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89S53 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
Page 34
... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89S53 34 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...