AT89C4051-24SI Atmel, AT89C4051-24SI Datasheet - Page 7
![IC MCU 2K FLASH 24MHZ 20-SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
AT89C4051-24SI
Manufacturer Part Number
AT89C4051-24SI
Description
IC MCU 2K FLASH 24MHZ 20-SOIC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C4051-12SU.pdf
(19 pages)
Specifications of AT89C4051-24SI
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C4051-24SI
Manufacturer:
ATMEL
Quantity:
5 530
Company:
Part Number:
AT89C4051-24SI
Manufacturer:
ATMEL
Quantity:
6 250
Company:
Part Number:
AT89C4051-24SI
Manufacturer:
ALTERA
Quantity:
590
Part Number:
AT89C4051-24SI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9. Idle Mode
10. Power-down Mode
11. Brown-out Detection
1001F–MICRO–6/08
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external
pullups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
In the power-down mode the oscillator is stopped and the instruction that invokes power-down is
the last instruction executed. The on-chip RAM and Special Function Registers retain their val-
ues until the power-down mode is terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before V
enough to allow the oscillator to restart and stabilize.
P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external
pullups are used.
When V
pulled high. When V
delay of typically 15 msec. The nominal brown-out detection threshold is 2.1V ± 10%.
CC
INTERNAL RESET
drops below the detection threshold, all port pins (except P1.0 and P1.1) are weakly
PORT PIN
CC
CC
is restored to its normal operating level and must be held active long
goes back up again, an internal Reset is automatically generated after a
V
CC
2.1V
2.1V
15 msec.
AT89C4051
7