PIC17LC44-08/P Microchip Technology, PIC17LC44-08/P Datasheet - Page 140
![IC MCU OTP 8KX16 PWM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC17LC44-08/P
Manufacturer Part Number
PIC17LC44-08/P
Description
IC MCU OTP 8KX16 PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Specifications of PIC17LC44-08/P
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC17LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
454 B
Interface Type
SCI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17LC44-08/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC17LC44-08/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C4X
TLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS30412C-page 140
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
t
RAM
TBLAT
RAM
TBLAT
t
RAM
TBLAT
RAM
TBLAT
Q1
=
=
=
=
=
=
=
=
=
=
register 'f'
Table Latch Write
[ label ] TLWT t,f
0
t
If t = 0,
If t = 1,
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
If t = 1; high byte is written
If t = 0; low byte is written
This instruction is used in conjunction
with TABLWT to transfer data from data
memory to program memory.
1
1
TLWT
None
Read
1010
Q2
f
f
0
0xB7
0x0000
0xB7
0x00B7
1
0xB7
0x0000
0xB7
0xB700
[0,1]
f
255
TBLATL;
TBLATH
t, RAM
01tx
(TBLATL = 0x00)
(TBLATL = 0xB7)
(TBLATL = 0x00)
(TBLATL = 0x00)
(TBLATH = 0x00)
(TBLATH = 0x00)
(TBLATH = 0x00)
(TBLATH = 0xB7)
Execute
Q3
ffff
TBLATH or
TBLATL
register
Write
Q4
ffff
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
Forced NOP
Decode
PC = Address(HERE)
If CNT
If CNT
Q1
Q1
PC
PC
register 'f'
Test f, skip if 0
[ label ] TSTFSZ f
0
skip if f = 0
None
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and an NOP is executed
making this a two-cycle instruction.
1
1 (2)
HERE
NZERO
ZERO
Read
NOP
0011
Q2
Q2
=
=
=
f
1996 Microchip Technology Inc.
255
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ
:
0011
Execute
Execute
Q3
Q3
CNT
ffff
NOP
NOP
Q4
Q4
ffff
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