PIC17C766-16I/PT Microchip Technology, PIC17C766-16I/PT Datasheet - Page 62
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C766-16I/PT
Manufacturer Part Number
PIC17C766-16I/PT
Description
IC MCU OTP 16KX16 A/D 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C766-16I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
66
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000, DM173001
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C766-16I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
8.2
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
8.2.1
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is automat-
ically incremented (for the next write). In Example 8-1,
the TBLPTR register is not automatically incremented.
FIGURE 8-5:
DS30289B-page 62
Table Writes to External Memory
Note: If external write and GLINTD = ’1’ and Enable bit = ’1’, then when ’1’
TABLE WRITE CODE
The highest pending interrupt is cleared.
AD15:AD0
Instruction
Instruction
Executed
Fetched
TABLWT WRITE TIMING (EXTERNAL MEMORY)
ALE
WR
OE
OE
Q1 Q2 Q3 Q4
’1’
INST (PC-1)
TABLWT
PC
Q1 Q2 Q3 Q4
TABLWT cycle1
INST (PC+1)
PC+1
EXAMPLE 8-1:
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
MOVLW
TABLWT
Data write cycle
Q1 Q2 Q3 Q4
TABLWT cycle2
TBL
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
LOW (DATA)
0,0,WREG
Flag bit, do table write.
Data out
Q1 Q2 Q3 Q4
TABLE WRITE
INST (PC+2)
INST (PC+1)
2000 Microchip Technology Inc.
PC+2
;
; Clear WDT
;
;
;
; Load HI byte
;
; Load LO byte
;
;
;
program memory
address
in TABLATH
in TABLATL
and write to
(Ext. SRAM)
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