PIC17C42A-25I/PT Microchip Technology, PIC17C42A-25I/PT Datasheet - Page 89
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PIC17C42A-25I/PT
Manufacturer Part Number
PIC17C42A-25I/PT
Description
IC MCU OTP 2KX16 PWM 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C42A-16P.pdf
(4 pages)
Specifications of PIC17C42A-25I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
4KB (2K x 16)
Program Memory Type
OTP
Ram Size
232 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AC164315 - MODULE SKT MPLAB PM3 44TQFPAC174005 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C42A-25I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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13.2
In this mode, the USART uses standard nonre-
turn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit). The most common data for-
mat is 8-bits. An on-chip dedicated 8-bit baud rate gen-
erator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmit-
ter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Par-
ity is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
13.2.1
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one T
TXREG is empty and an interrupt bit, TXIF (PIR<1>) is
set. This interrupt can be enabled or disabled by the
TXIE bit (PIE<1>). TXIF will be set regardless of TXIE
and cannot be reset in software. It will reset only when
new data is loaded into TXREG. While TXIF indicates
the status of the TXREG, the TRMT (TXSTA<1>) bit
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty.
1996 Microchip Technology Inc.
Note:
CY
USART Asynchronous Mode
USART ASYNCHRONOUS TRANSMITTER
at the end of the current BRG cycle), the
The TSR is not mapped in data memory,
so it is not available to the user.
Transmission
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 13-5). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 13-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the
RA5/TX/CK pin will revert to hi-impedance.
In
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to the
TXREG. This is because a data write to TXREG can
result in an immediate transfer of the data to the TSR
(if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the opposite
order.
Note:
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Load data to the TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN (starts
transmission).
order
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
re-enabled.
to
proper
is
select
enabled
state
9-bit
PIC17C4X
when
by
transmission,
DS30412C-page 89
setting
transmit
the
the
is
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