PIC16LC924-04I/SP Microchip Technology, PIC16LC924-04I/SP Datasheet - Page 2
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PIC16LC924-04I/SP
Manufacturer Part Number
PIC16LC924-04I/SP
Description
IC MCU 64 LD LOW 64-SDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC924-04I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
PIC16C924
4. Module: SSP Module (I
5. Module: SSP (SPI™ Mode)
EXAMPLE 1:
DS80111B-page 2
WAIT
If the bus is active when the I
and the next 8 bits of data on the bus match the
address of the device, then the SSP module will
generate an Acknowledge pulse.
Work around
Before enabling the I
is not active.
The Synchronous Serial Port module in SPI Mas-
ter mode only, allows the transmission of 1 byte of
data at a time. The module must be disabled and
then re-enabled between each byte transmission.
Work around
Once the SSP module has been configured in SPI
Master mode and one byte of data has been trans-
mitted, wait for the interrupt flag bit SSPIF
(PIR1<3>) or BF (SSPSTAT<0>) to be set. This
indicates that the byte of data has been transmit-
ted. Then, disable the SSP by clearing the SSPEN
bit of the SSPCON register. Re-enable the SSP by
setting the SSPEN bit. The SPI module will now
transmit the next data byte written to SSPBUF.
Refer to Example 1 for sample code.
When the SSP is disabled, the PORTC data latch
value is placed on the pins. The value in bit 3 of
PORTC (SCK) should have the same value as the
idle state of SCK. For example, if the clock idles
high, then bit 3 of PORTC must be set high. If bit
3 of PORTC is not configured the same as the idle
state of the clock, you may experience an addi-
tional clock when the SPI is disabled then re-
enabled.
MOVWF SSPBUF
BSF
BTFSS PIR1,
GOTO
BCF
BCF
BSF
STATUS,RP0
WAIT
STATUS,RP0
SSPCON,SSPEN
SSPCON,SSPEN
DISABLING AND
RE-ENABLING THE SSP
SSPIF
2
C mode, ensure that the bus
2
;data byte is
;in W register
;change to bank1
;wait for xmit
;buffer to empty
;change to bank0
;disable SSP
;enable SSP
C™ Mode)
2
C mode is enabled,
6. Module: SSP (SPI Mode)
FIGURE 1:
EXAMPLE 2:
7. Module: Timer0
LOOP BTFSS SSPSTAT, BF
When the SPI is using Timer2/2 as the clock
source, a shorter-than-expected SCK pulse may
occur on the first bit of the transmitted/received
data (see Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit, and then turn Timer2
back on. Refer to Example 2 for sample code.
The TMR0 register may increment when the WDT
postscaler is switched to the Timer0 prescaler. If
TMR0 = FFh, this will cause TMR0 to overflow
(setting T0IF).
Work around
Follow the following sequence:
a) Read the 8-bit TMR0 register into the
b) Clear the TMR0 register.
c) Assign WDT postscaler to Timer0.
d) Write W register to TMR0.
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
BCF
CLR
MOVWF SSPBUF
BSF
W register.
SD0
SCK
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
T2CON, TMR2ON
TMR2
T2CON, TMR2ON
Write SSPBUF
SCK PULSE VARIATION
USING TIMER 2/2
bit0=1 bit1=0 bit2=1 . . . .
SHORT SCK PULSE
AVOIDING THE INITIAL
2001 Microchip Technology Inc.
;Bank 1
;Data received?
;(Xmit complete?)
;No
;Bank 0
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on