PIC16LC774-I/P Microchip Technology, PIC16LC774-I/P Datasheet - Page 50
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PIC16LC774-I/P
Manufacturer Part Number
PIC16LC774-I/P
Description
IC MCU OTP 4KX14 A/D PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC774-I/P
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC774-I/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16LC774-I/PT
Manufacturer:
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Quantity:
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PIC16C77X
7.3
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 7-4
module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see
FIGURE 7-4:
A PWM output
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
FIGURE 7-5:
DS30275A-page 50
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
Note:
CCPR1L
CCPR1H (Slave)
Comparator
Duty cycle registers
TMR2 = PR2
PR2
or 2 bits of the prescaler to create 10-bit time-base.
TMR2
Comparator
PWM Mode
Duty Cycle
shows a simplified block diagram of the CCP
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
(Figure
Period
(Note 1)
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = Duty Cycle
Clear Timer,
CCP1 pin and
latch D.C.
7-5) has a time base (period)
TMR2 = PR2
CCP1CON<5:4>
Section
R
S
Q
7.3.3.
TRISC<2>
Advance Information
RC2/CCP1
7.3.1
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
7.3.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
For an example PWM period and duty cycle calcu-
lation, see the PICmicro™ Mid-Range Reference
Manual, (DS33023).
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
Note:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
PWM period = [(PR2) + 1] • 4 • T
PWM PERIOD
PWM DUTY CYCLE
The Timer2 postscaler (see
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
=
(TMR2 prescale value)
log
log(2)
Tosc • (TMR2 prescale value)
(
F
F
1999 Microchip Technology Inc.
PWM
OSC
)
OSC
bits
Section
•
6.0) is