PIC16C72AT-04E/SO Microchip Technology, PIC16C72AT-04E/SO Datasheet - Page 41

• Manufacturer Part Number: PIC16C72AT-04E/SO
• Description: IC MCU OTP 2KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72AT-04E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3
The SSP module in I
functions, except general call support, and provides
interrupts on start and stop bits in hardware to support
firmware implementations of the master functions. The
SSP module implements the standard mode specifica-
tions, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 8-2:
The SSP module has five registers for I
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not accessible
• SSP Address Register (SSPADD)
RC3/SCK/SCL
RC4/
1999 Microchip Technology Inc.
SDI/
SDA
SSP I
Read
2
clock
shift
C Operation
SSP BLOCK DIAGRAM
(I
2
MSb
2
C MODE)
C mode fully implements all slave
Stop bit detect
SSPBUF reg
Match detect
SSPADD reg
SSPSR reg
Start and
LSb
Write
(SSPSTAT reg)
Data Bus
2
Internal
C operation.
Set, Reset
S, P bits
Addr Match
Preliminary
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be operated as open
drain outputs, provided these pins are programmed to
inputs by setting the appropriate TRISC bits.
Additional information on SSP I
found in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
8.3.1
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
load the SSPBUF register with the received value in the
SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. This happens if
either of the following conditions occur:
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 8-2 shows what happens when a data transfer
byte is received, given the status of bits BF and SSPOV.
The shaded cells show the condition where user soft-
ware did not properly clear the overflow condition. Flag
bit BF is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
module, is shown in timing parameter #100, T
parameter #101, T
2
C specification, as well as the requirement of the SSP
stop bit interrupts enabled for firmware master
mode support
stop bit interrupts enabled for firmware master
mode support
ware master mode support, slave mode idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with start and
C Slave mode (10-bit address), with start and
C start and stop bit interrupts enabled for firm-
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was completed.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was completed.
SLAVE MODE
PIC16C62B/72A
LOW
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
.
2
C operation may be
DS35008B-page 41
2
HIGH
C opera-
, and