PIC16C72-04E/SS Microchip Technology, PIC16C72-04E/SS Datasheet - Page 104
![IC MCU OTP 2KX14 A/D PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C72-04E/SS
Manufacturer Part Number
PIC16C72-04E/SS
Description
IC MCU OTP 2KX14 A/D PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C72-04SO.pdf
(125 pages)
5.PIC16C72-04SO.pdf
(8 pages)
Specifications of PIC16C72-04E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
For Use With
309-1025 - ADAPTER 28-SSOP TO 28-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C72-04SO PDF datasheet #3
- PIC16C72-04SO PDF datasheet #4
- PIC16C72-04SO PDF datasheet #5
- Current page: 104 of 289
- Download datasheet (3Mb)
PIC16C7X
12.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
FIGURE 12-3: RX PIN SAMPLING SCHEME. BRGH = 0 (PIC16C73/73A/74/74A)
FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A)
FIGURE 12-5: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A)
DS30390E-page 104
Q2, Q4 clk
(RC7/RX/DT pin)
baud clk
RX pin
x4 clk
SAMPLING
baud CLK
x16 CLK
RX
Q2, Q4 clk
RX pin
baud clk
1
x4 clk
2
First falling edge after RX pin goes low
3
1
4
5
1
Start Bit
Samples
First falling edge after RX pin goes low
6
2
Samples
7
Samples
Second rising edge
3
Start Bit
8
2
4
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
9
Second rising edge
Start bit
1
Samples
10
Baud clk for all but start bit
bit0
2
11
Baud CLK for all but start bit
12
3
3
13
4
14
1
Samples
1997 Microchip Technology Inc.
bit1
15
2
16
1
4
2
Bit0
3
bit0
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