PIC16C62A-10/SS Microchip Technology, PIC16C62A-10/SS Datasheet - Page 106
![IC MCU OTP 2KX14 PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C62A-10/SS
Manufacturer Part Number
PIC16C62A-10/SS
Description
IC MCU OTP 2KX14 PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C62A-04SP.pdf
(8 pages)
Specifications of PIC16C62A-10/SS
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
For Use With
309-1025 - ADAPTER 28-SSOP TO 28-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C62A-04SP PDF datasheet #4
- Current page: 106 of 337
- Download datasheet (3Mb)
PIC16C6X
FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
DS30234D-page 106
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W-0
SPEN
SPEN: Serial Port Enable bit
(Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins when bits TRISC<7:6> are set)
1 = Serial port enabled
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data (Can be parity bit)
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
FERR
R-0
OERR
R-0
RX9D
R-x
bit0
R
W
U
- n = Value at POR reset
x
1997 Microchip Technology Inc.
= Writable bit
= Unimplemented
bit, read as ‘0’
= unknown
= Readable bit
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