PIC12C672T-04E/SM Microchip Technology, PIC12C672T-04E/SM Datasheet - Page 236
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PIC12C672T-04E/SM
Manufacturer Part Number
PIC12C672T-04E/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672T-04E/SM
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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PICmicro MID-RANGE MCU FAMILY
15.4
DS31015A-page 15-16
SSP I
2
C Operation
The SSP module in I
and provides interrupts on start and stop bits in hardware to facilitate software implementations
of the master functions. The SSP module implements the standard mode specifications as well
as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin,
which is the data. The user must configure these pins as inputs through the TRIS bits. The SSP
module functions are enabled by setting SSP Enable bit, SSPEN (SSPCON<5>).
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 15-7:
SSP Block Diagram (I
2
C mode fully implements all slave functions, except general call support,
SCL
SDA
Appendix A
Read
clock
shift
MSb
2
C Mode)
Stop bit detect
Match detect
SSPADD reg
SSPBUF reg
gives an overview of the I
SSPSR reg
Start and
LSb
Write
(SSPSTAT reg)
data bus
Internal
Set, Reset
S, P bits
Address Match
1997 Microchip Technology Inc.
2
C bus specification.
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