AT90S8535-8PC Atmel, AT90S8535-8PC Datasheet - Page 62
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AT90S8535-8PC
Manufacturer Part Number
AT90S8535-8PC
Description
IC MCU 8K FLSH 8MHZ A/D 40DIP
Manufacturer
Atmel
Series
AVR® 90Sr
Specifications of AT90S8535-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90S8535-8PC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
UART Control
UART I/O Data Register – UDR
UART Status Register – USR
62
AT90S/LS8535
The UDR register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data register is written. When
reading from UDR, the UART Receive Data register is read.
The USR register is a read-only register providing information on the UART status.
• Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift reg-
ister to UDR. The bit is set regardless of any detected framing errors. When the RXCIE
bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is
set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used,
the UART Receive Complete Interrupt routine must read UDR in order to clear RXC,
otherwise a new interrupt will occur once the interrupt routine terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift register has been shifted out and no new data has been written to UDR. This flag is
especially useful in half-duplex communications interfaces, where a transmitting appli-
cation must enter receive mode and free the communications bus immediately after
completing the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete
interrupt to be executed. TXC is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical
“1” to the bit.
• Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift
register. Setting of this bit indicates that the transmitter is ready to receive a new charac-
ter for transmission.
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe-
cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven
data transmission is used, the UART Data Register Empty Interrupt routine must write
UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou-
tine terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
• Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-
ing character is zero.
Bit
$0C ($2C)
Read/Write
Initial Value
Bit
$0B ($2B)
Read/Write
Initial Value
MSB
RXC
R/W
R
7
0
7
0
R/W
TXC
R/W
6
0
6
0
UDRE
R/W
R
5
0
5
1
R/W
FE
R
4
0
4
0
R/W
OR
R
3
0
3
0
R/W
R
2
0
2
–
0
R/W
R
1
0
1
–
0
LSB
R/W
R
0
0
0
–
0
1041H–11/01
UDR
USR