AT90S8535-8AI Atmel, AT90S8535-8AI Datasheet - Page 56

• Manufacturer Part Number: AT90S8535-8AI
• Description: IC MCU 8K 8MHZ A/D IT 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SS Pin Functionality
Data Modes
56
AT90S/LS8535
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine
the direction of the SS pin. If SS is configured as an output, the pin is a general output
pin, which does not affect the SPI system. If SS is configured as an input, it must be held
high to ensure master SPI operation. If the SS pin is driven low by peripheral circuitry
when the SPI is configured as master with the SS pin defined as an input, the SPI sys-
tem interprets this as another master selecting the SPI as a slave and starting to send
data to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a
2. The SPIF flag in SPSR is set and if the SPI interrupt is enabled and the I-bit in
Thus, when interrupt-driven SPI transmission is used in Master Mode and there exists a
possibility that SS is driven low, the interrupt should always check that the MSTR bit is
still set. Once the MSTR bit has been cleared by a slave select, it must be set by the
user to re-enable the SPI Master Mode.
When the SPI is configured as a slave, the SS pin is always input. When SS is held low,
the SPI is activated and MISO becomes an output if configured so by the user. All other
pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once
the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI
will stop sending and receiving immediately and both data received and data sent must
be considered as lost.
There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 39 and Figure 40.
Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0
result of the SPI becoming a slave, the MOSI and SCK pins become inputs.
SREG are set, the interrupt routine will be executed.
(FOR REFERENCE)
(FROM MASTER)
SS (TO SLAVE)
(FROM SLAVE)
SCK (CPOL=0)
SCK (CPOL=1)
SCK CYCLE#
SAMPLE
MOSI
MISO
*Not defined but normally MSB of character just received.
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
LSB
LSB
8
*
1041H–11/01