AT90S8535-8AC Atmel, AT90S8535-8AC Datasheet - Page 15
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AT90S8535-8AC
Manufacturer Part Number
AT90S8535-8AC
Description
IC MCU 8K FLSH 8MHZ A/D 44TQFP
Manufacturer
Atmel
Series
AVR® 90Sr
Specifications of AT90S8535-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90S8535-8AC
Manufacturer:
ROHM
Quantity:
6 934
Part Number:
AT90S8535-8AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Indirect Program Addressing,
IJMP and ICALL
Relative Program Addressing,
RJMP and RCALL
EEPROM Data Memory
Memory Access Times
and Instruction
Execution Timing
1041H–11/01
Figure 18. Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Figure 19. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is from -
2048 to 2047.
The AT90S8535 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 51 specifying the EEPROM address registers, the
EEPROM data register and the EEPROM control register.
For the SPI data downloading, see page 99 for a detailed description.
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power-unit.
+1
AT90S/LS8535
$FFF
$FFF
15